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ISL6622
Gate Voltage Optimization Technology (GVOT)
The ISL6622 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. During light
load operation, the switching losses dominate system
performance. Dropping down to a lower drive voltage with
GVOT during light load operation can reduce the switching
losses and maximize system efficiency.
Figure 2 shows that the gate drive voltage optimization is
accomplished via an internal low drop out regulator (LDO)
that regulates the lower gate drive voltage. LVCC is driven to
a lower voltage depending on the state of the internal PSI
signal and the GD_SEL pin impedance. The input and
output of this internal regulator is the VCC and LVCC pins,
Figure 3 illustrates the internal LDO’s variation with the
average load current plotted over a range of temperatures
spanning from -40 ° C to +120 ° C. Should finer tweaking of this
LVCC voltage be necessary, a resistor (R CC ) can be used to
shunt the LDO, as shown in Figure 2. The resistor delivers
part of the LGATE drive current, leaving less current going
through the internal LDO, elevating the LDO’s output
voltage. Further reduction in RCC’s value can raise the
LVCC voltage further, as desired.
Figure 4 also details the typical LDO performance when the
pass element is fully enhanced, as it is the case when the
driver operates in CCM.
12.0
respectively. Both VCC and LVCC should be decoupled with
a high quality low ESR ceramic capacitor.
11.8
VCC = 12V
+40°C
EXTERNAL CIRCUIT
ISL6622 INTERNAL CIRCUIT
SET BY
11.6
VIN >
RCC
VCC
1μF
GVOT
LDO
+
-
PSI AND
GD_SEL
+
-
11.4
11.2
11.0
LVCC
LGATE
10.8
1μF
DRIVER
10.6
0
20
40
60
80
100
RCC = OPTION FOR HIGHER LVCC
THAN PRE-SET BY GD_SEL
AVERAGE LOAD CURRENT (mA)
FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD (CCM)
FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL
9.0
In the 8 Ld SOIC package, the ISL6622 drives the upper and
lower gates close to VCC during normal PWM mode, while
8.5
+40°C
the lower gate drops down to a fixed 5.75V during PSI mode.
The 10 Ld DFN part offers more flexibility: the upper gate can
be driven from 5V to 12V via the UVCC pin, while the lower
8.0
7.5
GD_SEL TIED TO GND
+40°C
+120°C
-40°C
gate has a resistor-selectable drive voltage of 5.75V, 6.75V,
+120°C
-40°C
and 7.75V during PSI mode. This provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses. Table 1 shows
the LDO output (LVCC) level set by the PWM input and
GD_SEL pin impedance.
7.0
6.5
6.0
5.5
GD_SEL 4.5k Ω TO GND
GD_SEL FLOATING
+40°C
+120°C -40°C
TABLE 1. LDO OPERATION AND OPTIONS
PWM INPUT
GD_SEL PIN
LVCC @ 50mA DC LOAD
5.0
0
20
40 60 80
100
5V
0V
2 .5 V
Floating
4.5k Ω to GND
GND
5.75V (Typical; Fixed in
SOIC Package)
6.75V (Typical)
7.75V (Typical)
AVERAGE LOAD CURRENT (mA)
FIGURE 4. TYPICAL LVCC VARIATION WITH LOAD (DEM)
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds rising POR threshold,
5V
DON’T CARE
11.20V (Typical)
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the POR
falling threshold, operation of the driver is disabled.
0V
7
FN6470.2
October 30, 2008
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